RB203-02 : קורס בינה מלאכותית ו FPGA
https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/examples/led.html
https://learn.lushaylabs.com/tang-nano-9k-debugging/
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// ============================================================ // www.robotronix.co.il // Project: Single LED Blink // Description: // This program toggles one LED ON and OFF every 0.5 second. // Clock frequency: 27 MHz // LED type: active-low // active-low means: // led = 0 -> LED ON // led = 1 -> LED OFF // ============================================================ module led ( input sys_clk, // 27 MHz system clock input output reg led // single LED output ); // ------------------------------------------------------------ // Counter maximum value for 0.5 second delay // 27,000,000 clock cycles = 1 second // 13,500,000 clock cycles = 0.5 second // // Because counting starts from 0: // last count value = 13,500,000 - 1 = 13,499,999 // ------------------------------------------------------------ localparam CNT_MAX = 24'd13_499_999; // 24-bit counter // 24 bits are enough because: // 2^24 = 16,777,216 reg [23:0] counter = 24'd0; // Initial LED state // 1 means LED OFF for active-low LED initial begin led = 1'b1; end // ------------------------------------------------------------ // Main logic // This block runs on every rising edge of sys_clk // ------------------------------------------------------------ always @(posedge sys_clk) begin // Count clock cycles until 0.5 second passes if (counter < CNT_MAX) begin counter <= counter + 1'b1; end // When 0.5 second passed else begin counter <= 24'd0; // reset counter to 0 led <= ~led; // toggle LED state end end endmodule |
דוגמא לקוד מתקדם יותר FPGA יותר לדים וקלט של RESET
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module led ( input sys_clk, // clock input input sys_rst_n, // reset input, active low output reg [5:0] led // 6 LED pins ); // For 27 MHz clock: // 27,000,000 clocks = 1 second // 13,500,000 clocks = 0.5 second localparam CNT_MAX = 24'd13_499_999; reg [23:0] counter; // counter for 0.5 second delay always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) counter <= 24'd0; else if (counter < CNT_MAX) counter <= counter + 1'b1; else counter <= 24'd0; end // rotate LED pattern every 0.5 second always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) led <= 6'b111110; // first LED ON, active-low else if (counter == CNT_MAX) led <= {led[4:0], led[5]}; // rotate left end endmodule |
